(1) Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a pair of transistors which should have the same electrical characteristic, such as a differential amplifier.
(2) Description of the Related Art
FIG. 1 is an equivalent circuit diagram illustrating a conventional differential amplifier. Referring to FIG. 1, a differential amplifier 1 has an input stage 2 and an output stage 3. The input stage 2 comprises a first pair of transistors Qa and Qb, a second pair of transistors Qc and Qd and a constant-current source J. The transistors Qa and Qb are so-called differential pair transistors (differential input transistors). Emitters of the differential pair transistors Qa and Qb are connected to each other and the constant-current source J is connected to the emitters thereof. Collectors of the second pair of transistors Qc and Qd are respectively connected to collectors of the first pair of transistors Qa and Qb so that the second pair of transistors Qc and Qd function as a constant-current load of the differential pair transistors Qa and Qb. The second pair of transistors Qc and Qd form a current mirror circuit, and the transistors Qc and Qd are so-called current mirror transistors. Bases of the differential pair transistors Qa and Qb are connected to input terminals (an inverting input terminal and a non-inverting terminal) 5 and 6 between which signals are supplied. Emitters of the current mirror transistors Qc and Qd are connected to a power source terminal 4, and the output unit 3 is connected to the collectors of the transistors Qb and Qd so that a voltage in accordance with a voltage of a signal supplied between the input terminals 5 and 6 is output from an output terminal 7 thereof.
In the above differential amplifier, it is desired that no DC offset voltage be output from the output terminal 7 under a condition in which a voltage between the input terminals 5 and 6 (the bases of the differential pair transistors Qa and Qb) is equal to zero. The DC offset voltage depends on the difference between forward drop characteristics in base-emitter junctions of the differential pair transistors Qa and Qb. Thus, both the differential pair transistor Qa and Qb are generally made on a single semiconductor chip so as to have the same electrical characteristics (including the forward drop characteristics in the base-emitter junctions).
However, it is difficult to obtain differential pair transistors having exactly the same electrical characteristics. Due to the variations of plane shapes of elements of each transistor which variation is caused by the mask resolution and due to the variation of a semiconductor characteristic (a resistivity) in a direction parallel to a surface of a semiconductor chip which variation is caused by irregularities in a diffusion process, the electrical characteristic of each transistor is varied.
It has been known that the above variation caused by the mask resolution can be reduced by increasing the size of each transistor in a direction parallel to the surface of the semiconductor chip. It has been also known that the above variation caused by the irregularities in the diffusion process can be reduced by forming the differential pair transistors as shown in FIGS. 2A and 2B.
Referring to FIG. 2A, each of the differential pair transistors Qa and Qb is formed of two transistor elements. That is, a first transistor Qa out of the differential pair transistors Qa and Qb is formed of transistor elements Q1 and Q4 which are connected to each other in parallel and a second transistor Qb out of the differential pair transistors Qa and Qb is formed of transistor elements Q2 and Q3 which are connected to each other in parallel. The above four transistors Q1, Q2, Q3 and Q4 are formed on a semiconductor chip so as to be arranged as shown in FIG. 2B. This arrangement of the transistors Q1, Q2, Q3 and Q4 are often referred to as a common-centroid layout. Referring to FIG. 2B, the transistor elements Q1 and Q4 forming the first transistor Qa are arranged on a semiconductor chip so as to be symmetrical about a center point O, and the transistor elements Q2 and Q3 forming the second transistor Qb are arranged on the semiconductor chip, in a direction perpendicular to a direction in which the transistor elements Q1 and Q4 are arranged, so as to be symmetrical about the center point O. Furthermore, the transistor elements Qt and Q2 are symmetrical about a y-axis, the transistors Q3 and Q4 are symmetrical about the y-axis, the transistors Q1 and Q3 are symmetrical about an x-axis perpendicular to the y-axis, and the transistors Q2 and Q4 are symmetrical about the x-axis.
In the differential pair transistors Qa and Qb having the above construction in accordance with the common-centroid layout as shown in FIG. 2B, the location of the transistor element Q1 is the same as those of the transistor elements Q2 and Q3 respectively in directions of the y-axis and the x-axis, and the location of the transistor element Q4 is the same as those of the transistor elements Q2 and Q3 respectively in directions of the x-axis and the y-axis. Thus, even if the semiconductor chip has the gradient of the resistivity in a direction parallel to the x-axis, the electrical characteristics of the transistor elements Q1 and Q4 are respectively similar to those of the transistors Q3 and Q2. In addition, even if the semiconductor chip has the gradient of the resistivity in a direction parallel to the y-axis, the electrical characteristics of the transistor elements Q1 and Q4 are respectively similar to those of the transistors Q2 and Q3. As a result, even if the semiconductor chip has the gradient of the resistivity in any direction, the electric characteristic of the first transistor Qa formed of the transistors Q1 and Q4 is similar to that of the second transistor Qb formed of the transistors Q2 and Q3.
However, the equality of the differential transistors Qa and Qb in the electric characteristic is not sufficient to further reduce the offset voltage in the differential amplifier 1.